1. Field of the Invention
The present invention relates to a semiconductor device including a MOS (Metal Oxide Semiconductor) field effect transistor (hereinafter referred to as xe2x80x9cSOI-MOSFETxe2x80x9d) formed in a semiconductor layer on an insulator such as an insulator substrate and a method of manufacturing the same, and, more particularly, to a technique for improving withstand voltage and current driving characteristics between source and drain regions.
2. Description of the Background Art
FIG. 1 is a sectional view of a SOI-MOSFET as a first conventional example. Referring to FIG. 1, the SOI-MOSFET includes an insulator layer 2 formed on a silicon substrate 1 and a silicon layer 3 formed on insulator layer 2. A channel forming region 6 having a low concentration of p-type impurities (1016-1017/cm3, for example) is formed in silicon layer 3, and an additional source region 7a and an additional drain region 8a having a concentration of n-type impurities (1017-1018/cm3, for example) are formed respectively in contact with the left and right sides of channel forming region 6. A source region 7b and a drain region 8b having a high concentration of n-type impurities concentration (1019-1021//cm3, for example) are formed respectively adjacent to additional source region 7a and additional drain region 8a. 
A gate insulating film 4 is formed on channel forming region 6, and a gate electrode 5 is formed on gate insulating film 4. Sidewalls 13 are provided on the sidewalls of gate electrode 5 on additional source region 7a and additional drain region 8a. Silicon layer 3 and gate electrode 5 are covered with an interlayer insulating film 9. Contact holes 10a, 10b are provided in interlayer insulating film 9, and corresponding conductors, i.e. a source electrode 11 and a drain electrode 12 in this case, are formed in respective contact holes 10a, 10b. 
If positive voltage is applied to gate electrode 5 in a SOI-MOSFET constituted as described above, n-type carriers (electrons) are induced to the upper part of p-type channel forming region 6, and the upper part is inverted to be the same n-type as additional source region 7a, additional drain region 8a, source region 7b, and drain region 8b. Accordingly, current can flow between source region 7b and drain region 8b. In addition, the concentration of the n-type carriers induced to upper part of channel forming region 6 changes in accordance with the gate voltage, so that it is possible to control the current flowing in channel forming region 6 with the gate voltage. This is the operation principle of the MOSFET.
The reason why additional source region 7a and additional drain region 8a were formed respectively adjacent to source region 7b and drain region 8b in the first conventional thin film SOI-MOSFET having the above-described structure is as described in the following.
In a case where it is a thin film SOI-MOSFET having silicon layer 3 of approximately 300 xc3x85-1500 xc3x85, even if additional source region 7a and additional drain region 8a are not formed, the whole of channel forming region 6 is easily made to be a depletion layer by applying voltage to gate electrode 5, and the potential of the channel forming region is also controlled by the gate electrode, so that so-called punch through or short channel effect is reduced. Here, xe2x80x9cpunch throughxe2x80x9d is a phenomenon that a depletion layer extending from drain region 8b into channel forming region 6 reaches to source region 7b, the electric barrier between source region 7b and channel 6 is lowered, and the channel current is suddenly increased by it. xe2x80x9cShort channel effectxe2x80x9d is a phenomenon that when the gate length is short, the gate threshold voltage becomes extremely low.
However, if the whole of channel forming region 6 is completely depleted, the potential in channel forming region 6 becomes higher than that in the case of a conventional bulk MOSFET. Accordingly, the electric barrier between source region 7b and channel forming region 6 is lowered, and holes generated by so-called impact ionization, a phenomenon that highly accelerated electrons collide with a lattice in the vicinity of drain region 8b and cause electrons and holes to be generated, come to be temporarily stored in channel forming region 6. As a result, the potential in channel forming region 6 is further raised, and electrons are suddenly injected from source region 7b into channel forming region 6. Specifically, in a case where additional source region 7a and additional drain region 8a are not formed in a thin film SOI-MOSFET expected as a short channel MOSFET, the withstand voltage between the source and the drain tends to be lowered. FIG. 4A shows the drain currentxe2x80x94drain voltage characteristics of the thin film SOI-MOSFET in this case.
In order to prevent such lowering of the withstand voltage between the source and the drain, a so-called LDD (Lightly Doped Drain) structure is constituted by providing a low second conductivity-type additional drain region 8a between drain region 8b and channel forming region 6 in a normal thin film SOI-MOSFET such as the first conventional example described above to reduce the electric field in the vicinity of drain region 8b and prevent storage of holes caused by impact ionization so that the withstand voltage between the source and the drain is enhanced. Now, a method of manufacturing the above-described first conventional thin film SOI-MOSFET will be described with reference to FIGS. 2A-2E.
First, referring to FIG. 2A, a silicon layer 3 is formed on a silicon substrate 1 with an insulator layer 2 interposed therebetween. Specific manufacturing methods in this case normally include SIMOX (Separation by Implanted Oxygen) in which oxygen ions are implanted in silicon substrate 1 and a silicon oxide film is formed directly in silicon substrate 1.
Next, silicon layer 3 is patterned into a shape of an island, and p-type impurities such as boron are introduced by an ion implantation process or the like to make the concentration 1016-1017/cm3, for example, to form a channel forming region 6 (FIG. 2B).
A gate insulating film 4 is formed on silicon layer 3 by a thermal oxidation process or the like, and a gate electrode material such as polycrystalline silicon is deposited by a CVD method. A resist 14 is patterned on the polycrystalline silicon by a photolithography process, and the polycrystalline silicon is etched using the resist 14 to form a gate electrode 5.
Next, n-type impurities such as phosphorus are introduced into silicon layer 3 using gate electrode 5 and resist 14 as a mask to make the concentration 1017-1018/cm3 to form an additional source region 7a and an additional drain region 8a (FIG. 2C).
Next, a silicon oxide film 13a is deposited by a CVD method (FIG. 2D), anisotropic etching is carried out on silicon oxide film 13a by a reactive ion etching process to form a sidewall spacer 13 on the sidewalls of gate electrode 5. Next, n-type impurities such as phosphorus or arsenic are ion-implanted in silicon layer 3 using gate electrode 5 and sidewall spacer 13 as a mask, and a source region 7b and a drain region 8b are formed to have a concentration of 1019-1021/cm3, for example (FIG. 2E).
An interlayer insulating film 9 is formed, then contact holes 10a, 10b are formed by a reactive ion etching process, for example, and conductive interconnection layers 11, 12 including aluminum or the like are formed to complete the structure illustrated in FIG. 1.
As described above, the above first conventional thin film SOI-MOSFET has the concentration of additional source region 7a and additional drain region 8a lowered to approximately 1017/cm3 in order to enhance the withstand voltage between the source and the drain by electric field reduction. Therefore, the carrier concentration is lowered, the resistance of additional source region 7a and additional drain region 8a is increased, and a significant decline in the current driving capability is caused as shown in FIG. 4B.
Japanese Patent Laying-Open No. 60-133756 (1985) discloses a thin film SOI-MOSFET having a so-called gate overlap type LDD structure (hereinafter referred to as xe2x80x9ca second conventional examplexe2x80x9d), for example, for improving the problems in the first conventional example.
A thin film SOI-MOSFET of the second conventional example has low concentration impurity regions, which are additional source/drain regions, overlapped with the region of a gate electrode. This causes the gate voltage to be directly applied to the additional source/drain regions, so that it is possible to raise the carrier concentration of the additional source/drain regions at the same time that the conductivity type of the channel forming region is inverted when the MOSFET is on operation. Accordingly, it is possible to prevent deterioration of the current driving characteristics caused by increase of the resistance value of the additional source/drain regions having a low concentration.
Now, a method of manufacturing the thin film SOI-MOSFET of the second conventional example will be described with reference to FIGS. 3A to 3E.
First, referring to FIG. 3A, an insulator layer 22 is formed on an insulating substrate 21, and then a semiconductor layer 23 is formed.
Next, referring to FIG. 3B, semiconductor layer 23 is patterned, and then a gate insulating layer 24 is formed. Then, referring to FIG. 3C, a gate electrode 25 having the resistance reduced by thermal diffusion of impurities or the like is formed, and then a resist layer 26 is etched so that it has the same width as the channel width and has a length shorter than the channel length by several percent as illustrated in FIG. 3C to form a mask for ion implantation as illustrated in FIG. 3C.
Next, referring to FIG. 3D, ion implantation is carried out by irradiating impurity ions 27 using resist layer 26 as a mask, and then heat treatment is carried out to activate the impurities.
Then, referring to FIG. 3E, resist layer 26 is removed, and an interlayer insulating layer 28 is formed. Contact holes are formed, and then electrodes 29 are formed. The concentration of an additional source/drain region 30 formed by ion implantation is lower than that of the region of a source/drain region 31 adjacent to it; This is because implantation of impurity ions into additional source/drain region 30 is carried out through gate electrode 25, so that the amount of the implanted ions is reduced in accordance with effects of the thickness of gate electrode 25.
However, according to the manufacturing method as described in the above second conventional example, ion implantation for forming additional source/drain region 30 is carried out through gate electrode 25, so that a step of forming resist layer 26 is required, and the process becomes complicated. In addition, the concentration of additional source/drain region 30 is controlled by the thickness of gate electrode 25, so that it is liable to be affected by diversification of the thickness or the material of gate electrode 25. In the case of a thin film SOI-MOSFET of a LDD structure having an additional source/drain region overlapping with gate electrode 25, it is necessary to set the concentration of the additional source/drain region to a value in a certain limited range with high precision in order to obtain satisfactory transistor characteristics. However, there was no disclosure of a concentration setting in the above second conventional example, and fine control of the concentration of the additional source/drain region was difficult.
One object of the present invention is to provide a semiconductor device including a gate overlap-type thin film SOI-MOSFET having an optimum concentration of an additional source/drain region for having satisfactory transistor characteristics and a method of manufacturing the same.
In order to solve the above described problems, a semiconductor device according to the present invention includes a semiconductor layer having a thickness of 300 xc3x85 to 1500 xc3x85 formed on an insulator layer and a gate electrode formed on the semiconductor layer with a gate insulating film interposed therebetween. A pair of additional source/drain regions of a first conductivity type is formed from immediately beneath both of right and left side ends of the gate electrode inward in the semiconductor layer in the region immediately beneath the gate electrode, and a channel forming region of a second conductivity type is formed in the semiconductor layer in a region between the pair of additional source/drain regions. Further, a pair of source/drain regions of the first conductivity type is formed adjacent to the end opposite the side in contact with the channel forming region of the additional source/drain regions in the semiconductor device.
The additional source/drain regions in the semiconductor device have an impurity concentration of 3xc3x971017 to 3xc3x971018/cm3, and the source/drain region has an impurity concentration higher than that of the additional source/drain regions.
According to the semiconductor device of the present invention, gate overlap-type additional source/drain regions are included, and the concentration is set to 3xc3x9710173xc3x971018/cm3, so that it has functions as described in the following.
In a case where the gate electrode is 0V, and a predetermined positive bias voltage is applied to the drain region, substantially only the whole of additional source/drain regions is depleted because the additional source/drain regions are set to have a concentration of 3xc3x971018/cm3 or less. As a result, the electric field strength reduction effect is larger as compared to the case where the concentration of the additional source/drain regions is too high to sufficiently deplete the additional source/drain regions or the case where the concentration is so low as to cause depletion to proceed up to the adjacent source/drain regions. Further, it also has effects unique to a gate overlap structure, so that satisfactory transistor characteristics can be obtained. If the concentration of the additional source/drain region is set to less than 3xc3x971017, the parasitic resistance thereof affects the properties of the device.
According to a method of manufacturing a semiconductor device of the present invention, first, a gate insulating film is formed on a semiconductor layer on an insulator layer, and a gate electrode is formed on the gate insulating film. Next, impurities of a first conductivity type are introduced just beneath the vicinity of the ends of the gate electrode in the semiconductor layer by implanting the impurities from a predetermined direction making a predetermined angle of inclination with the surface of the semiconductor layer using the gate electrode as a mask to form additional source/drain regions. Subsequently, impurities of the first conductivity type are implanted from a direction perpendicular to the surface of the semiconductor layer onto the semiconductor layer using the gate electrode as a mask to form source/drain regions.
According to the above-described manufacturing method, the additional source/drain regions are formed by ion implantation using only the gate electrode as a mask, so that it is not necessary to separately pattern the mask as in the above second conventional example, and the manufacturing process is simplified.
According to another aspect of the method of manufacturing a semiconductor device of the present invention, the step of forming the additional source/drain regions is carried out by forming a gate electrode on the gate insulating film, then introducing impurities of a first conductivity type by ion implantation using the gate electrode as a mask, and then diffusing the impurities beneath the gate electrode by predetermined heat treatment.
According to this manufacturing method, formation of the additional source/drain regions is carried out by oblique ion implantation using the gate electrode as a mask, so that it is possible to set the length of the overlap of the additional source/drain regions with the gate electrode or the impurity concentration with higher precision as compared to the case where it is carried out by thermal diffusion.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.